(1) Field of the Invention
The present invention relates to combination memory devices and semiconductor devices, and in particular to a combination memory device provided with a static random access memory (SRAM) and a read only memory (ROM).
(2) Description of the Related Art
In recent years, the degree of integration of system LSIs has been improving every year along with higher performance of sets and finer processes. In particular, a remarkable improvement can be seen in an amount of a volatile memory such as a static random memory (hereinafter referred to as SRAM or RAM) installed in the system LSI, and a non-volatile memory such as a read only memory (hereinafter referred to as ROM), a flash memory, and the like.
The volatile memory and the non-volatile memory are combined in installation in the system LSI and a one-chip microcomputer. The area of the combination memory region used for the volatile memory and the non-volatile memory in the system LSI and the one-chip microcomputer is relatively large compared to the entire area of the system LSI and the one-chip microcomputer. Thus, the area of a semiconductor chip is determined by how much the area of the combination memory region is miniaturized.
To this end, Patent Reference 1: Japanese Unexamined Patent Application Publication No. 63-53798 discloses a combination memory device provided with a memory cell including an SRAM and a ROM.
FIG. 19 shows a configuration of a combination memory device 900 described in Patent Reference 1. The combination memory device 900 as shown in FIG. 19 includes memory cells 910 arranged in a matrix.
FIG. 20 is a circuit diagram which shows a configuration of the memory cell 910.
As shown in FIG. 20, the memory cell 910 includes an SRAM cell 120 and a ROM cell 930. The SRAM cell 120 and the ROM cell 930 are connected to a common word line 140. Further, the SRAM cell 120 is connected to RAM bit lines 141A and 141B, and the ROM cell 930 is connected to a ROM bit line 942.
Further, the ROM cell 930 stores data that is determined by forming or not forming a contact 931 that connects the ROM cell 930 and the ROM bit line 942, for example.
As described above, the conventional combination memory device 900 includes the SRAM and the ROM in the same cell to share an address. With this, the combination memory device 900 has the following three advantages: (i) reduction of costs for an address selection circuit and other peripheral circuits (area reduction); (ii) more flexible processing of a microcomputer by switching between the SRAM and the ROM for an operation; and (iii) implementation of a new feature by installing, on the ROM, a system program of the microcomputer, a test program, or the like which can not be used by a user.
However, although Patent Reference 1 allows area reduction of the peripheral circuits, it is not described in Patent Reference 1 to reduce area of a memory cell region. In other words, there is no description regarding what layout is used to form the memory cell 910.
Here, the area of the combination memory device is determined depending mainly on the area of the memory cell region. More specifically, compared to the case where the SRAM and the ROM are formed separately, how much the area of the memory cell region can be reduced contributes greatly to area reduction of the combination memory device.    Patent Reference 1: Japanese Unexamined Patent Application Publication No. 63-53798 (page 6, FIG. 1)